外文翻譯--- - 利用梳狀濾波器設計多速率濾波器

1、<p><b>　　附錄A</b></p><p>　　Multirate Filter Designs Using Comb Filters</p><p>　　SHUN1 CHU, MEMBER, IEEE, AND C. SIDNEY BURRUS, FELLOW, IEEE</p><p>　　Abstract-Results

2、 on multistage multirate digital filter design indicate most of the stages can be designed to control aliasing with only slight regard for the passband which is controlled by a single stage compensator. Because of this,

3、the aliasing controlling stages can be made very simple. This paper considers comb filter structures for decimators and interpolators in multistage structures. Design procedures are developed and examples shown that have

4、 a very low multiplication rate, very few fi</p><p>　　Introduction</p><p>　　Multirate filters are members of a class which has different sampling rates in various stages of the filtering operati

5、on. This class of filters includes decimators, interpolators, and narrow-band low-pass filters implemented with decimation, low-pass filtering, and interpolation. A multistage implementation of these filters has the samp

6、le rate changed in several steps where each step is a combined filtering and sample rate change operation. Crochiere and Rabiner [1]-[4] gave the standard multist</p><p>　　Using the design described in [5] w

7、ith no passband specifications for each stage allows simple filters to be employed and gives a satisfactory frequency response. Let H(z) and D be the transfer function and decimation ratio of one stage of a multistage de

8、cimator. We propose to design H(z) such that H(z) = f(z)g(zD). In the implementation, by the commutative rule [5], the transfer function g(zD) can be implemented at the lower rate (after decimation) as g(z). This impleme

9、ntation reduces the filte</p><p>　　In this paper, to simplify arithmetic, further requirements are put on H(z) to allow only simple integer coefficients. This is feasible because there are no passband specif

10、ications on the frequency response. A cascade of comb filters is a particular case of these filters where the coefficients are only 1or-1 and, therefore, no multiplications are needed. Hogenauer [6] had also used a casca

11、de of comb filters as a one-stage decimator or interpolator but with a limited frequency-response characteri</p><p>　　The FIR filter optimizing procedure used in this paper minimizes the Chebyshev norm of th

12、e approximation error and this is done using the Remez exchange algorithm. The IIR filter optimizing procedure used minimizes the lp error norm which approaches the Chebyshev norm when p is large.</p><p>　　T

13、he New Multistage Multirate Digital Filter Design Method</p><p>　　In a paper for limited range DFT computation using decimation [7], Cooley and Winograd pointed out that the passband response of a decimator

14、can be neglected and be taken care of after decimation. A multistage multirate digital filter design method which has no passband specification but using passband and stopband gain difference as an aliasing attenuation c

15、riterion for each stage is described in [5]. The design method and equations used in that paper which are needed for the comb filter struct</p><p>　　The commutative rule introduced in [5] states that the fil

16、ter structures in Fig. l(a) and (b) are equivalent. It means that a filter can commute with a rate changing switch provided that the filter has its transfer function changed from H(z) to H(zD) or vice versa. Fig. 1 illus

17、trates the case for decimation, and it is also true for interpolation. This rule is very useful in finding equivalent multirate filter structures and in deriving the transfer function of a multistage multirate filter.<

18、;/p><p>　　For example, Fig. 2(a) shows the filter structure of a multistage decimator where frk, k = 0, 1, . . . , K, is the sampling rate at each stage, and a one-stage equivalent decimator shown in Fig. 2(b)

19、is found by repeatedly applying the commutative rule to move the latter stages forward. From the one-stage equivalent, it is clear that the transfer function and frequency response of the multistage decimator are</p&g

20、t;<p><b>　　(1)</b></p><p><b>　　and</b></p><p><b>　　(2)</b></p><p>　　where D = D1D2 . . . Dk. The filtering function of Hc(z) does not invo

21、lve a sampling rate change. It is used to compensate the passband frequency responses of previous stages, and hence, is called the compensator.</p><p>　　Each decimation stage is designed successively. At the

22、 time of designing the i th stage filter, all the previous i-1 stages have already been designed and the transfer functions known. The requirement on Hi(z) is that the composite frequency response HDi (w) of the first st

23、age to the i th stage have enough aliasing attenuation where </p><p><b>　　(3)</b></p><p>　　referenced to fr(i- 1) = 1. Enough aliasing attenuation means that those frequency componen

24、ts which will alias into the passband at the current decimation process will have adequate attenuation with respect to the corresponding passband components. Fig. 3 shows an example frequency response of HDi (w) which ha

25、s an aliasing attenuation exceeding 60 dB. In Fig. 3, the passband response is repeated in the stopbands but has been moved down by 60dB. They are used as the atttenuation bounds for the st</p><p>　　The over

26、all filter frequency response is Hc(w)HDK( w/DK) referenced to frK = 1. The design of the compensator transfer function is to make the overall frequency response approximate one in the passband. The frequency-response er

27、ror in the passband is</p><p><b>　　(4)</b></p><p>　　for To give attenuation to the first band that will alias to the transition band, it is required that for , or equivalently,for

28、. The frequency bandcan be considered as the stopband of the compensator and the frequency-response error is </p><p><b>　　(5)</b></p><p>　　for . Equations (4) and (5) can be combined

29、 to give an error function of</p><p><b>　　(6)</b></p><p>　　and , which is the error weighting of the stopband with respect to the passband. The optimal HC(z) is obtained by minimizin

30、g the error norm ||E|| of (6). The solution depends on the definition of the norm.</p><p>　　The multistage interpolator design is the same as the multistage decimator design but with the filter structure rev

31、ersed.</p><p>　　The multirate low-pass filter structure is a multistage decimator followed by a multistage interpolator and, in between, there is a compensator operated at the lowest sampling rate with no ra

32、te change. If the aliasing attenuation requirement for the decimator is the same as the imaging attenuation requirement for the interpolator, the design of the multistage decimator part and that of the interpolator part

33、can be the same. The overall frequency response is </p><p><b>　　(9)</b></p><p>　　where </p><p><b>　　(10)</b></p><p>　　Hi(w) is the frequ

34、ency response of each decimator (or interpolator) stage and “mod” means a modulo operation. The frequency response of (9) is the output baseband response due to the whole input in terms of the input frequency as in the c

35、ase of decimator. It is also the output response due to the baseband input in terms of the output frequency as in the case of interpolator.</p><p>　　In the multirate low-pass filter design, each decimation o

36、r interpolation stage design is the same as that in a multistage decimator design. The compensator is to give the desired frequency response in the baseband where the baseband is the frequency band that never aliases. It

37、s design is to minimize ||E|| of (6) with the weighting and desired functions given by</p><p>　　In the case where there is not a full decimation, i.e., referenced to frK =1, there is a stopband for the comp

38、ensator design. The transition region can also be viewed as the stopband of the compensator with requirement to limit the transition region aliasing.</p><p>　　Comb filter structures as decimators or interpol

39、ators</p><p>　　This section exploits some simple efficient filter structures which can be used in the decimation or interpolation stages of the multistage multirate filter. The requirement on these filters i

40、s that they have enough aliasing attenuation such as shown in the example frequency response of Fig. 3. Since the operation and structure of an interpolator are the duals of a decimator, most explanation in this section

41、will be for the decimator case only. Extension to the interpolator case is simple and </p><p>　　Let H(z) and D be the transfer function and decimation ratio for one stage of a multistage decimator. The fil

42、ter structure is shown in Fig. 4(a). One method to make the filter efficient is to design H(z) such that it has the form</p><p><b>　　(13)</b></p><p>　　and the factor g(zD) can be imp

43、lemented at the lower rate as g(z) as shown in Fig. 4(b). By this implementation, a high-order H(z) can be implemented at the low rate as a low-order filter. The arithmetic rate, number of filter coefficients, and number

44、 of registers used are, therefore, reduced. Further improvement in arithmetic rate can be achieved by simplifying the filter coefficients of f(z) and g(z) in (13) to be simple integers and using additions instead of mult

45、iplications.</p><p>　　One example of this kind of filter is a cascade of comb filters. We will show some filter structures first and discuss the filter operations in the next section.</p><p>　　A

46、 comb filter of length D is an FIR filter with all D coefficients equal to one. The transfer function of this comb filter is</p><p><b>　　(14)</b></p><p>　　A comb filter with length D

47、 followed by decimation with a ratio D is shown in Fig. 5(a). The commutative rule can be applied to the numerator to get the structure of Fig. 5(b).The new comb decimator structure needs two registers, one addition at t

48、he high rate, and one addition at the low rate regardless of the decimation ratio D, i.e., the filter length.</p><p>　　The comb interpolator structure is shown in Fig. 5(c). It is the reverse of the decimato

49、r structure with the sampler replaced by a zero padder. The realization of the transfer function l/(1-z-l) is an accumulator. Since the accumulator has D-1 out of every D inputs as zero, it can take advantage of this to

50、accumulate only once for every D inputs. This is equivalent to operating the accumulator at the lower rate and each output is used D times at the higher rate. When the accumulator is moved to </p><p>　　A sin

51、gle comb filter generally will not give enough stopband attenuation, however, cascaded comb filters can often meet requirements. Cascading M length-D comb filters will have a transfer function</p><p><b&g

52、t;　　(15)</b></p><p>　　Fig. 6(a) shows a comb decimator with M length-D comb filters in cascade where all the: accumulators are cascaded before the sampler and all the (1-z-1) sections are cascaded afte

53、r the sampler. When the reverse of the structure of Fig. 6(a) is used as an interpolator, one of the comb filters can be realized as a sample and hold switch. This interpolator structure is shown in Fig. 6(b). </p>

54、;<p>　　In a multistage decimator design, a latter stage usually needs more comb filters in cascade to give adequate stopband attenuation because of the relatively wider stopband(s) and narrower transition region.

55、Fig. 7(a) shows an equivalent three-stage comb decimator structure. The first, second, and the third stages have three, four, and five length-D1, length-D2, and length-D3, comb filters in cascade, respectively. Fig. 7(b)

56、 shows the corresponding equivalent comb interpolator structure using samp</p><p><b>　　附錄B</b></p><p>　　利用梳狀濾波器設計多速率濾波器</p><p>　　摘要-多級多速率數字濾波器設計成果表明大多數階段可以被用來控制抗鋸齒，只有輕微的

57、通頻帶由一個單一的階段補償。正因為如此，抗鋸齒控制階段可以很簡單。本文認為，梳狀濾波器結構可以設計成decimators和interpolators多級結構。設計程序的開發(fā)和事例表明，有繁殖率非常低，只有極少數濾波器系數，低存儲需求，以及簡單的結構。</p><p><b>　　緒論</b></p><p>　　多速率濾波器的成員，其中一類在各個階段的過濾操作具有不同

58、的采樣率。這一級別的過濾器包括decimators，interpolators，和窄帶低通濾波器實施抽取，低通濾波和插值。一個多執(zhí)行這些過濾器的采樣率改變了若干步驟，每個步驟是合并過濾和采樣率的變化作業(yè)。Crochiere和Rabiner [1]-[4]的標準多了設計方法，這些過濾器而每個階段作為一個低通濾波器在一個最佳的選擇抽取（或內插法）的比例在每一階段。一種設計方法是在[5]采用不同的設計標準，每一個階段。它不僅要求每個階段有足夠

59、的抗鋸齒衰減，但沒有通規(guī)格。</p><p>　　使用中所描述的設計[5]沒有通規(guī)格的每一個階段可以簡單的過濾器，采用并給出了一個令人滿意的頻率響應。設H(z)和D是傳遞函數和抽取一個階段比一個多decimator。我們建議設計的H(z)等認為H(z)= F(z)*g(zD)。在執(zhí)行時，由交換規(guī)則[5]，轉移函數g(zD)可以實現在較低的利率（后抽?。間(z)的。這降低了過濾器執(zhí)行命令，存儲要求，算術。<

60、/p><p>　　本文簡化算法，提出了進一步要求的H(z)的，只允許簡單的整數系數。這是可行的，因為沒有通規(guī)格的頻率響應。一連串梳狀濾波器是一種特定情況下，這些過濾器的系數只有1或者-1 ，因此，沒有乘法是必要的。 Hogenauer [6]也采用了級聯梳狀濾波器作為一期decimator或插值，但有限的頻率響應特性。在這里，級聯梳狀濾波器是用來作為一個階段的多級多速率濾波器的權利與公正的頻率響應。梳狀濾波器結構更容

61、易產生利用交換規(guī)則。</p><p>　　FIR濾波器的優(yōu)化程序，本文件中使用的切比雪夫準則最小的逼近誤差，這是使用雷米茲交換算法。IIR濾波器的優(yōu)化程序，最大限度地減少使用規(guī)范低壓錯誤做法的切比雪夫時， p是規(guī)范。</p><p>　　新型多級多速率數字濾波器的設計方法</p><p>　　在一份文件中對有限范圍的DFT計算使用抽取[7] ，利和維諾格拉德指出通響

62、應decimator可以忽略不計，并得到照顧后抽取。多級多速率數字濾波器的設計方法，沒有通規(guī)范，但使用通和阻增益差異作為走樣衰減標準的每個階段中所描述[5] 。的設計方法和公式中所用文件，該文件所需要的梳狀濾波器結構本節(jié)概述。</p><p>　　交換規(guī)則的介紹[ 5 ]指出，過濾器結構圖。1(a)和(b)是相同的。這意味著，一個過濾器可以改判率變化與交換機的過濾提供了其傳遞函數的變化從H (z)至H(zD)，反

63、之亦然。圖1顯示的情況抽取，也是真正的插值。這條規(guī)則是非常有用的在尋找相當于多過濾器的結構和所產生的傳遞函數的多級多速率濾波器。</p><p>　　例如，圖2(a)顯示了過濾器結構的多級decimator。圖中,frk= 0，1…，K，是采樣率在每一個階段，和一階段相當于decimator顯示圖2(b)發(fā)現的反復運用移動交換規(guī)則后期向前發(fā)展。從一期當量，可以清楚地看到，傳遞函數和頻率響應的是多級decimato

64、r。</p><p><b>　　(1)</b></p><p><b>　　(2)</b></p><p>　　其中D = D1,D2…, Dk。過濾功能HC(z)的不涉及采樣率的變化。它是用來補償通頻率響應前階段，因此，所謂的補償。</p><p>　　每個階段的目的是抽取先后。當時設計的I階段

65、過濾器，所有以前的i-1階段已經設計和傳遞函數眾所周知的。要求高科技Hi(z)的是，在綜合頻率響應HDi(W)的第一階段至I次階段有足夠的混淆在衰減</p><p><b>　　(3)</b></p><p>　　參照fr（i-1）= 1 。足夠的抗鋸齒衰減意味著這些高頻成分將別名納入通目前抽取過程將有足夠的衰減對相應的通元件。圖3顯示一個例子頻率響應的發(fā)展行動HDi

66、(w)，其中有一個別名衰減超過60分貝。圖3通響應中重復stopbands，但已被移至下跌六零分貝。它們被用來作為atttenuation和stopbands的邊界。如果阻響應低于這些跨越，它將有足夠的抗鋸齒衰減。</p><p>　　總過濾器的頻率響應是Hc(w)HDK( w/DK)。參照frK = 1 。設計補償傳遞函數是使總的頻率響應近似一個在通頻帶。頻率響應誤差是</p><p>

67、<b>　　(4)</b></p><p>　　對于為了讓第一波段衰減，化名過渡帶，要求對于當于對于。頻帶可視為阻的補償和頻率響應誤差</p><p><b>　　(5)</b></p><p>　　對于 方程(4)和(5)可以合并成一個錯誤功能</p><p><b>　　(6)<

68、;/b></p><p><b>　　。</b></p><p>　　多級插補設計是一樣的設計，但多decimator的過濾器結構扭轉。</p><p>　　在多低通濾波器的結構是一個多decimator隨后多插值，并在之間，有一種補償操作的最低采樣率沒有變動。如果走樣衰減要求decimator是一樣的成像衰減要求插補，設計的多級deci

69、mator的一部分，并且部分的插值可以是相同的?？偟念l率響應是</p><p><b>　　(9)</b></p><p><b>　　(10)</b></p><p>　　Hi(w)是頻率響應每個decimator （或插值）的階段， “絕對值”是指模作業(yè)。頻率響應的(9)是輸出的基帶響應由于整個投入方面的輸入頻率，如d

70、ecimator。這也是輸出響應由于基投入方面的輸出頻率，如插值。</p><p>　　在多低通濾波器的設計，每個抽取或插值舞臺設計是一樣的，在一個多decimator設計。補償是使所期望的頻率響應的基帶的基帶是頻段從未別名。其設計是為了盡量減少| |E| |的(6)的加權和期望的職能。</p><p>　　在沒有整數倍取樣率降低的情況下，不存在一個完整的抽取，即參照frK = 1 ，有阻

71、的補償設計。過渡地區(qū)也可以被視為阻的補償要求，以限制過渡區(qū)走樣。</p><p>　　梳狀濾波器結構用于decimators或細分器</p><p>　　本節(jié)利用一些簡單有效的過濾器結構，用于抽取或內插階段的多級多速率濾波器。對這些過濾器的要求是，它們有足夠的抗鋸齒衰減，如范例中頻率響應圖所示。由于操作和結構插值是decimator的雙排氣管系統(tǒng)，本節(jié)的大多數解釋將只是decimator的

72、案例。插值的擴展案例將是很簡單和直接的。</p><p>　　設H(z)和D是一個多級decimator的做為一個階段的傳遞函數和抽取比例。該過濾器的結構如圖所示。一種方法是制作高效的過濾器將H(z)設計成如下形式：</p><p>　　系數可以以低速率應用于，如圖4所示。根據這一實施，一個高階的H(z)可以以低速率應用于低階的濾波器。因此，算術率，濾波器系數和一些寄存器的使用會隨之減少。

73、通過簡化公式(13)中的濾波器系數f(z)和g(z)，可以達到進一步改善算術率的目的。使用簡單的整數和補充替代乘法器。</p><p>　　這種濾波器的一個例子是一種級聯式梳狀濾波器。首先我們展示一些濾波器的結構，在下一章討論濾波器的操作。</p><p>　　梳狀濾波器的長度D是一個FIR濾波器的所有D系數的和。梳狀濾波器的傳遞函數如下：</p><p>　　梳狀

74、濾波器的長度D，其次是抽取如圖5(a)所示的系數D。這種交替規(guī)則可以應用到計數器來得到如圖5(b)所示的結構。新型梳狀結構需要兩個寄存器，一個以高速率工作，一個不顧濾波器長度抽取速率D而以低速率工作。</p><p>　　梳狀插入器結構如圖5(c)所示。這是一個反向的decimators和被一個微調電容器取代的采樣器。轉移功能l/(1-z-l)的實現是累加器。由于累加器來自每個D的D-1為零，它可以利用這個只有一

75、次的積累投入到每一個D。這相當于以較低的速率操作累加器，而以高速率輸出用于D的時間。當累加器被轉移至低速率時，取消了l/(1-z-l)節(jié)，保留交換器僅作為一個梳狀插入器，如圖5(d)所示。區(qū)分采樣保持開關的采樣開關decimator并指明采樣率增加后，采樣保持開關，采樣保持開關是由一個常閉開關。該交換規(guī)則可應用于整個采樣保持開關，因為它適用于當有一個速度的變化。</p><p>　　一個單一的梳狀濾波器一般不會給

76、予足夠的阻帶衰減，但是，級聯梳狀濾波器往往滿足要求。級聯M長度三維梳狀濾波器將有一個傳遞函數</p><p>　　圖6(a)顯示了decimator與M長度三維梳狀濾波器的級聯：累加器級聯采樣之前，所有的l/(1-z-l)節(jié)級聯后采樣。當扭轉的結構圖6(a)被用作插值，一個梳狀濾波器，才能實現作為采樣保持開關。這插補結構如顯示圖6(b)所示。</p><p>　　在一個多decimator

77、設計，后一階段通常需要更多的梳狀濾波器的級聯給予充分阻帶衰減，因為相對更廣泛的阻帶和狹義的過渡區(qū)域，圖7(a)所示。相當于三個階段decimator結構。第一，第二，第三階段的三，四，五長度- D1型，長度- D2中，D3 ，梳狀濾波器的級聯。圖7(b)列出了相應的等效梳插結構使用采樣保持開關。這些相當于結構得到了應用交換規(guī)則。由于傳播l/(1-z-l)節(jié)，有些(1/l/(1-z-l))節(jié)和l/(1-z-l)取消了對方。這種多級梳狀濾波